EtherCAT Slave HAL

Version  Name  Date       Revision History
2.4.0.0  AOC   05.12.2019 Changed: BUILD to 26
                          Bugfix (netX100/500 only): corrected MII.TX output_phase negedge+3 to posedge+2
                          Bugfix: DC time control loop not working correctly if difference >=1 seconds
                          Bugfix: flag "WRITE_REQ" not reset in function Esc_SiiSetWriteFailed()
                          Bugfix: flag "READ_REQ" not reset in function Esc_SiiSetReadFailed()

2.3.0.0  AOC   04.11.2019 Changed: BUILD to 25
                          In case of link lost: RX error counters are saturated to 0xff (EtherCAT registers 0x301, 0x0303)

2.2.0.6  IOS   17.04.2019 Added support for netX90 Revision 1 (no changes in HAL/XC)

2.2.0.5  AOC   11.03.2019 Added: internal function EscCfgMii() to support external PHYs connected to XC1 on netX4000 and netX90
                          Added: support for XC1 on netX4000

2.2.0.4  BIL   26.11.2018 Added support for netX90, removed support for netX90MPW
                          Added support for NXHX4100_JTAG Revision 1

2.2.0.3  AOC   28.11.2017 Bugfix: Sync Manager queued state not reset during initialisation (not netX100/500)
                          Bugfix: Sync Manager queued/buffered state not reset under all circumstances in function "Esc_SetSyncManDisByAl()" (not netX100/500)
                          Added support for NXHX4000_JTAG_PLUS Revision 3 (support of previous revisions dropped)

2.2.0.2  AOC   08.06.2017 Changed: BUILD to 24 (netX100/500 only)
                          Bugfix (netX100/500 only): Transmitted frame divided into 2 fragments in rare cases when host issues one of following requests during Ethernet header of EtherCAT frame receiving
                                                     - RX_PDO exchange
                                                     - TX_PDO exchange
                                                     - PDI Watchdog Triggered

2.2.0.1  IOS   02.04.2017 Added support for NXHX4000_SWITCH

2.2.0.0  AOC   15.02.2017 Added support for netX4000 and netX90
                          Changed: BUILD to 23
                          Bugfix: sometimes additional nibble sent in case of non-EtherCAT frames forwarded in conjunction with DL_CONTROL.Ecat_only=0

2.1.0.0  AOC   08.04.2016 Changed: BUILD to 22
                          Re-insert: PDI Watchdog functionality, but Watchdog value must not configured manually by host (as done in previous HAL versions)

2.0.0.0  AOC   08.03.2016 Merging all netX derivates to netX Studio project (Hitex Hitop IDE support dropped)




### Older release notes ###

Hardware platform:
NXHX500-RE (EtherCAT Slave on XC channel 0/1/3)
NXIO (EtherCAT Slave on XC channel 0/1/3)

Version  Name  Date       Revision History
0.900    AOC   -          created
0.901    AOC   -          several small bug fixes
0.902    SBO   -          fix of physical read/write to sync manager protected area
0.903    SBO   -          Corrected DC Control Loop when using 64Bit DC (see comments in Esc_Dc.c)
1.0.0.0  AOC   24.02.2009 Initial release for Subversion and NXHX-Board
                          Change: it it not possible to disable DC functionality anymore
                          Bugfix: Corrected DC Control Loop for re-sync
                          Change: DC Control Loop and DC reset processed in xPEC instead on ARM
                          Bugfix: Corrected DC Diff value calculation in case of wrap-around between global and local time
                          Added: EEPROM content increased, so master does not need xml to get slave running
                          Changed: increasing of PDO size to 464 bytes overall
                          Added: PDO size adjustable due DIP switch settings during power-up
                          Changed: BUILD to 6
                          Changed: Sync signal length from 256 to 1 s
                          Changed: SII CRC to 0x88A4 (disabled)
                          Changed: ESI (Product code, Second VendorID)
                          successfully tested with Ecat conformance tool release V1.0.0.17
1.2.0.0  AOC   15.04.2010 Changed: BUILD to 7
                          Changed: NextSync0/1SystemTimeNs now updated in runtime
                          Changed: Previous Errors not counted anymore
                          Changed: Feature register updated to actual specification
                          Bugfix: ESC hangs up after link down in case of high net load
                          Changed: some changes in project structure
                          Bugfix: FMMU 1 Configuration not invalid after Restart by EtherCAT Master und SyncManager Disable by AL
                          Bugfix: Register Impulse Length 0x982..0x983 changed from writable to read-only
                          Successfully tested with Ecat conformance tool release V1.20.0.0
                          Added: DL_CONTROL and DL_STATUS readable via PDI function Esc_ReadReg
1.3.0.0  AOC   09.07.2010 Changed: BUILD to 8
                          Bugfix: SrcMac[1] only set in processing direction if DlCtrl.EcatOnly==1 (instead in both directions)
                          Bugfix: Non Ecat Frames only destroyed in processing direction of DlCtrl.EcatOnly==1 (instead in both directions)
                          Bugfix: Closed port in mode "AutoClose" opens loop after frame with valid CRC is received
                          Bugfix: Handling of circulating frames changed (depends on Loop Closed instead of No Link)
                          Changed: "hal_resources_defines.h" modified to avoid warnings during compilation
                          Changed: Clarification of DC modes "Synchronous with SYNC0 Event" and "Synchronous with SYNC1 Event"
1.4.0.0  AOC   13.09.2010 Changed: BUILD to 9
                          Changed: DC PLL adjustment range extended from +/-150ppm to +/-750ppm
                          Added: PHY stati mapped into register ESCF_FLASH_FREQ_OF_LINK_ACT_TEMP (for generation of Link/Act LEDs manually on host side)
                          Added: Sync pins (xm3.io0/1) and ADC controllable by ARM
1.4.1.0  AOC   19.10.2010 Changed: BUILD to 10
                          Changed: Possibility to initialize without DC functionality to get XC port 3 free for user's stuff
1.4.2.0  AOC   19.01.2011 Correct entries in EtherCAT feature register
1.4.3.0  AOC   25.03.2011 Changed: Build to 11
                          Bugfix: IP/UDP header detection in forwarding direction
                          Bugfix: "esc_irq_lock" never locked interrupts
1.4.4.0  AOC   01.08.2011 Changed: Build to 12
                          Added: Variable Mailbox size supported
                          Added: extended Esc_ReadReg to read type, revision, build, FMMU number, SyncMan number, RAM size, features supported, port descriptor
                          Bugfix: Esc_SetSyncManDisByAl did not reset sync manager on disable
                          Changed: Simplified handling of Sync Manager configuration in Esc_FmmuSmConfigControl.c
                          Bugfix: Corrected code sequence in Esc_SmReWriteTxMailbox due to Bugfix in Esc_SetSyncManDisByAl
                          Added: 780 byte mailbox configuration with 32 Byte PDO each direction
                          Added: DC PI Controller parameters writable by Host
1.5.0.0  AOC   02.11.2011 Changed: Build to 13
                          Changed: Default DC Control algorithm has now same behavior as Beckhoff ASICs have
                                   Please Note:
                                   It is still possible to switch on Hilscher specific PI-based DC control algorithm of former HAL versions via HAL function "Esc_Initialize"
                                   The Hilscher specific PI-based DC Control algorithm introduces synchronization jitter in case of netX is reference clock and controlled by EtherCAT Master
                          Added: "Esc_Initialize" has additional parameter to select DC Control Algorithm
1.5.1.0  AOC   30.11.2011 Changed in main.c: No reload of "Configured Station Alias" when SII Reload requested (shall always be done via PowerUp)
                          Added in ESI (xml): set for all RxPDO and TxPDO the attribute mandatory=1
1.5.2.0  AOC   27.04.2012 Changed: Build to 14
                          Bugfix: No repair of corrupt frames in very rare cases of MII.RxDv goes down for a few MII.RxClk cycles
                          Added:  AL_STATUS bit 5 writable to support "Explicit Device Identification" via AL_STATUS
1.5.3.0  AOC   22.08.2012 Changed: Build to 15
                          Bugfix: Receive time stamping in case of processing via OUT port (f.e. when node is last one in line but connected to OUT port)
1.5.4.0  IOS   06.11.2012 Changed: Build to 16
                          Bugfix: wrong calculation of SysTime difference when master_clock wrapped
1.5.5.0  IOS   16.11.2012 Including string.h for memset declaration
                          Changed: Build to 17
                          Bugfix: WKC setting to 1 in case of SM3 not written
                          Added: support of NXHX500ETM_R02/NXHX500ETM_R03 Evaboard
1.6.0.0  BIL   13.11.2014 Changed: Refactoring of data types in HAL API
                          Changed: Reworked example application
1.7.0.0  AOC   05.02.2015 Changed: Build to 20
                          Removed: PDI Watchdog functionality
                          Removed: Hilscher specific PI-based DC control algorithm
                          Bugfix: Pos++ in case of APRW and BRW commands (was not done in older version)
                          Bugfix: ARMW: if Position Bit15 set then Command was ignored instead of writing
                          Added: ESC_EVENT_MSK Register shadowed
                          Added: FMMU and SyncManager Configuration Registers shadowed
                          Bugfix: Ethernet frame corruption when accessing physical register areas 0xa00..0xfff
                          Changed: Register 0x990 ("System time of next SYNC0 pulse in ns") and Register 0x998 ("System time of next SYNC1 pulse in ns") latched altogether when detecting read access at register area 0x980..0x9A7; Earlier ESC Builds latch both System times individually when detect read access to register address 0x990/0x998
                          Bugfix: Ethernet frame reception errors in case of Ethernet frame is VLAN-Tagged or with IP/UDP header in connection with large Ethernet clock drifts
                          Bugfix: Reset value of Station Address (Address 0x0010) changed from 0xdead to 0x0000
                          Bugfix: wrong Sync0/1 polarity when gap between disabling and re-enabling of CyclicUnit smaller than pulse width of Sync0/1
                          Bugfix: Mailbox SyncManager is disabled on conflicting PD SyncManager changes
                          Bugfix: DC StartTime CyclicOp (0x990..0x993) corrupted if read before activation of cyclic unit (0x981.0 = 1)
1.7.0.1  AOC   24.04.2015 Changed: Build to 21
                          Added: UDP-CRC set to 0x0000 in processing and forwarding direction
                          Added in ESI: <Mailbox DataLinkLayer="true">
                          Added within HAL Example: if DIP switch (ID-selector) set to zero then Configured Station Alias register (0x12) set to netX specific value (e.g. netX100/500: 500, netX50: 50, ...)
1.7.0.2  AOC   28.09.2015 Bugfix: ESI description incorrect entries
                          Changed: HAL documentation


Hardware platform:
NXHX50-RE (EtherCAT on XC channel 0/1)

Version  Name  Date       Revision History
1.0.0.0  AOC   24.02.2009 Initial release for Subversion and NXHX-Board
                          Change: it it not possible to disable DC functionality anymore
                          Bugfix: Corrected DC Control Loop for re-sync
                          Change: DC Control Loop and DC reset processed in xPEC instead on ARM
                          Bugfix: Corrected DC Diff value calculation in case of wrap-around between global and local time
                          Added: EEPROM content increased, so master does not need xml to get slave running
                          Changed: increasing of PDO size to 464 bytes overall
                          Added: PDO size adjustable due DIP switch settings during power-up
                          Changed: BUILD to 6
                          Changed: Sync signal length from 256 to 1 s
                          Changed: SII CRC to 0x88A4 (disabled)
                          Changed: ESI (Product code, Second VendorID)
                          successfully tested with Ecat conformance tool release V1.0.0.17
1.2.0.0  AOC   15.04.2010 Changed: BUILD to 7
                          Changed: NextSync0/1SystemTimeNs now updated in runtime
                          Changed: Latch functionality removed to allow NextSync0/1SystimeNs updating in runtime
                          Changed: Previous Errors not counted anymore
                          Changed: Feature register updated to actual specification
                          Bugfix: ESC hangs up after link down in case of high net load
                          Changed: some changes in project structure
                          Bugfix: Inconsistent mailbox content when polling mailbox via WKC
                          Bugfix: Register Impulse Length 0x982..0x983 changed from writable to read-only
                          Successfully tested with Ecat conformance tool release V1.20.0.0
                          Bugfix: Timer Interrupt Confirmation workaround included
                          Added: DL_CONTROL and DL_STATUS readable via PDI function Esc_ReadReg
1.3.0.0  AOC   09.07.2010 Changed: BUILD to 8
                          Bugfix: SrcMac[1] only set in processing direction if DlCtrl.EcatOnly==1 (instead in both directions)
                          Bugfix: Non Ecat Frames only destroyed in processing direction of DlCtrl.EcatOnly==1 (instead in both directions)
                          Bugfix: Closed port in mode "AutoClose" opens loop after frame with valid CRC is received
                          Bugfix: Handling of circulating frames changed (depends on Loop Closed instead of No Link)
                          Changed: "hal_resource_defines.h" modified to avoid warnings during compilation
                          Bugfix: Esc_SetSyncManDisByAl did not correctly re-enable BufferManager on 3 buffer write SyncMan
                          Bugfix: removed remains of Latch irq handling code in Example application and HAL header
                          Changed: Clarification of DC modes "Synchronous with SYNC0 Event" and "Synchronous with SYNC1 Event"
                          Added: support of NXIO50RE Evaboard
1.4.0.0  AOC   13.09.2010 Changed: BUILD to 9
                          Bugfix: data inconsistency in ESC memory through writing ESC memory although FMMU mismatch
                          Changed: DC PLL adjustment range extended from +/-150ppm to +/-750ppm
                          Added: PHY stati mapped into register ESCF_FLASH_FREQ_OF_LINK_ACT_TEMP (for generation of Link/Act LEDs manually on host side)
1.4.1.0  SBO   24.03.2011 Bugfix: in Esc_SetSyncManDisByAl: corrected 1ST_BUF_WRITE request
         AOC   25.03.2011 Changed: Build to 10
                          Bugfix: IP/UDP header detection in forwarding direction
                          Bugfix: "esc_irq_lock" never locked interrupts
                          Bugfix: in Esc_SetSyncManDisByAl: Reset Buffer Manager channel when Sync Manager disabled by AL
                          Bugfix: in Esc_UpdateSm: "Sync Manager disabled by AL" cleared when configuring Sync Manager
1.4.2.0  AOC   01.08.2011 Changed: Build to 11
                          Added: Variable Mailbox size supported
                          Added: extended Esc_ReadReg to read type, revision, build, FMMU number, SyncMan number, RAM size, features supported, port descriptor
                          Added: 780 byte mailbox configuration with 512 Byte PDO each direction
                          Added: DC PI Controller parameters writable by Host
1.5.0.0  AOC   02.11.2011 Changed: Build to 12
                          Changed: Default DC Control algorithmus has now same behaviour as Beckhoff ASICs have
                                   Please Note:
                                   It is still possible to switch on Hilscher specific PI-based DC control algorithmus of former HAL versions via HAL function "Esc_Initialize"
                                   The Hilscher specific PI-based DC Control algorithm introduces synchronization jitter in case of netX is reference clock and controlled by EtherCAT Master
                          Added: "Esc_Initialize" has additional parameter to select DC Control Algorithm
1.5.1.0  AOC   30.11.2011 Changed in main.c: No reload of "Configured Station Alias" when SII Reload requested (shall always be done via PowerUp)
                          Added in ESI (xml): set for all RxPDO and TxPDO the attribute mandatory=1
1.5.2.0  AOC   27.04.2012 Changed: Build to 13
                          Bugfix: No repair of corrupt frames in very rare cases of MII.RxDv goes down for a few MII.RxClk cycles
                          Added:  AL_STATUS bit 5 writable to support "Explicit Device Identification" via AL_STATUS
1.5.3.0  AOC   22.08.2012 Changed: Build to 14
                          Bugfix: Receive time stamping in case of processing via OUT port (f.e. when node is last one in line but connected to OUT port)
1.5.4.0  IOS   06.11.2012 Changed: Build to 15
                          Bugfix: wrong calculation of SysTime difference when master_clock wrapped
1.5.5.0  IOS   16.11.2012 Including string.h for memset declaration
                          Included Explicit Device Identification Example
                          Added: support of NXHX50ETM_R02 Evaboard
1.6.0.0  BIL   13.11.2014 Changed: Refactoring of data types in HAL API
                          Changed: Reworked example application
1.7.0.0  AOC   05.02.2015 Changed: Build to 20
                          Removed: PDI Watchdog functionality
                          Removed: Hilscher specific PI-based DC control algorithm
                          Bugfix: ARMW: if Position Bit15 set then Command was ignored instead of writing
                          Added: ESC_EVENT_MSK Register shadowed
                          Added: FMMU and SyncManager Configuration Registers shadowed
                          Bugfix: Ethernet frame corruption when accessing physical register areas 0xa00..0xfff
                          Changed: Register 0x990 ("System time of next SYNC0 pulse in ns") and Register 0x998 ("System time of next SYNC1 pulse in ns") latched altogether when detecting read access at register area 0x980..0x9A7; Earlier ESC Builds latch both System times individually when detect read access to register address 0x990/0x998
                          Bugfix: Ethernet frame reception errors in case of Ethernet frame is VLAN-Tagged or with IP/UDP header in connection with large Ethernet clock drifts
                          Bugfix: Reset value of Station Address (Address 0x0010) changed from 0xdead to 0x0000
                          Bugfix: Mailbox SyncManager is disabled on conflicting PD SyncManager changes
                          Bugfix: DC StartTime CyclicOp (0x990..0x993) corrupted if read before activation of cyclic unit (0x981.0 = 1)
1.7.0.1  AOC   24.04.2015 Changed: Build to 21
                          Added: UDP-CRC set to 0x0000 in processing and forwarding direction
                          Added in ESI: <Mailbox DataLinkLayer="true">
                          Added within HAL Example: if DIP switch (ID-selector) set to zero then Configured Station Alias register (0x12) set to netX specific value (e.g. netX100/500: 500, netX50: 50, ...)
1.7.0.2  AOC   28.09.2015 Bugfix: ESI description incorrect entries
                          Changed: HAL documentation


Hardware platform(s):
NXHX51(+NXHX6)
NXEB52RE
NXHX52RE

Version  Name  Date       Revision History
1.0.0.0  AOC   18.04.2012 Initial release
1.1.0.0  AOC   06.06.2012 Changed Mailbox ESC read/write calls to use the actual mailbox size value used by ESM to check mailbox parameters
                          Changed: access now DWORD only to improve access time for process data exchange (especially in netX6 use case)
                          Changed: all sync manager protected areas DWORD-aligned, added two examples to support non-DWORD multiple Sync manager length
                          added: netX6 support
                          added: RUN/ERR or STATUS LED controlled by ESC (xPEC); deleted software-based LED handler from main()
                          deleted: OSAL (now implemented by common_func.h/c)
                          requirement for IRQ locks checked and commented
                          added: irq_handler.h/c added to introduce public calls to ESC_ProcPortInterrupt/Esc_ProcPortInterrupt2/Esc_SyncPortInterrupt
                          structured SII image instead of fixed arrays
1.1.1.0  AOC   16.07.2012 Added support for HXHX52-RE
                          Removed double calls to Esm_WriteAlStatusByEsm
         AOC   22.08.2012 Changed: Build to 2
                          Bugfix: Receive time stamping in case of processing via OUT port (f.e. when node is last one in line but connected to OUT port)
1.1.2.0  AOC   29.08.2012 Deleted ALStatus Debug code
                          Bugfix: lost interrupts when using serial DPM due changing to level-triggered interrupt
                          Support of serial DPM with speed=50 MBaud
                          Bugfix: initialize DPM failed when compiled in "released" build instead of "debug" build
1.1.3.0  IOS   06.11.2012 Changed: Build to 3
                          Bugfix: wrong calculation of SysTime difference when master_clock wrapped
1.1.4.0  IOS   22.11.2012 updating HAL documentation
1.2.0.0  BIL   13.11.2014 Changed: Refactoring of data types in HAL API
                          Deleted: Esc_TriggerPdiWdg()
                          Changed: Reworked example application
1.3.0.0  AOC   05.02.2015 Changed: Build to 20
                          Removed: PDI Watchdog functionality
                          Removed: Hilscher specific PI-based DC control algorithm
                          Bugfix: ARMW: if Position Bit15 set then Command was ignored instead of writing
                          Added: ESC_EVENT_MSK Register shadowed
                          Added: FMMU and SyncManager Configuration Registers shadowed
                          Bugfix: Ethernet frame corruption when accessing physical register areas 0xa00..0xfff
                          Changed: Register 0x990 ("System time of next SYNC0 pulse in ns") and Register 0x998 ("System time of next SYNC1 pulse in ns") latched altogether when detecting read access at register area 0x980..0x9A7; Earlier ESC Builds latch both System times individually when detect read access to register address 0x990/0x998
                          Bugfix: Ethernet frame reception errors in case of Ethernet frame is VLAN-Tagged or with IP/UDP header in connection with large Ethernet clock drifts
                          Bugfix: Reset value of Station Address (Address 0x0010) changed from 0xdead to 0x0000
                          Removed: hardware support for RUN/ERR and STATUS LED driving
                          Bugfix: Mailbox SyncManager is disabled on conflicting PD SyncManager changes
                          Bugfix: DC StartTime CyclicOp (0x990..0x993) corrupted if read before activation of cyclic unit (0x981.0 = 1)
1.3.0.1  AOC   24.04.2015 Changed: Build to 21
                          Added: UDP-CRC set to 0x0000 in processing and forwarding direction
                          Added in ESI: <Mailbox DataLinkLayer="true">
                          Added within HAL Example: if DIP switch (ID-selector) set to zero then Configured Station Alias register (0x12) set to netX specific value (e.g. netX100/500: 500, netX50: 50, ...)
1.3.0.2  AOC   28.09.2015 Bugfix: ESI description incorrect entries
                          Changed: HAL documentation
